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cy14b101l 1 mbit (128k x 8) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-06400 rev. *m revised april 5, 2010 features 25 ns [1] , 35 ns, and 45 ns access times pin compatible with stk14ca8 hands off automatic store on power down with only a small capacitor store to quantumtrap nonvolatile elements is initiated by software, hardware, or autostore on power down recall to sram initiated by software or power up unlimited read, write, and recall cycles 200,000 store cycles to quantumtrap 20 year data retention at 55 c single 3v +20% , ?10% operation commercial and industrial temperature 32-pin (300 mil) soic and 48-pin (300 mil) ssop packages rohs compliance functional description the cypress cy14b101l is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles , while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. store/ recall control power control software detect static ram array 1024 x 1024 quantumtrap 1024 x 1024 store recall column io column dec row decoder input buffers oe ce we hsb v cc v cap a 15 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 11 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 logic block diagram note 1. 25 ns speed in industrial temperature range is over the operating voltage range of 3.3v+ 0.3v only. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 2 of 21 contents features ............................................................................... 1 functional description ....................................................... 1 logic block diagram .......................................................... 1 contents .............................................................................. 2 pinouts ................................................................................ 3 device operation ................................................................ 4 sram read ......................................................................... 4 sram write ......................................................................... 4 autostore operation .......................................................... 4 hardware store (hsb) operation ................................... 4 hardware recall (power up) .......................................... 5 software store ................................................................. 5 software recall ............................................................... 5 data protection ................................................................... 5 noise considerations ......................................................... 5 low average active power ................................................ 5 preventing store ................................................................. 6 best practices ..................................................................... 6 maximum ratings ............................................................... 8 operating range ................................................................. 8 dc electrical characteristics ............................................ 8 data retention and endurance .. ....................................... 8 capacitance ........................................................................ 9 thermal resistance ............................................................ 9 ac test conditions ............................................................ 9 sram read cycle ...................................................... 10 sram write cycle....................................................... 11 autostore or power up recall .................................... 12 software controlled store/recall cycle .................. 13 switching waveforms ...................................................... 14 part numbering nomenclature ........................................ 15 ordering information ........................................................ 15 package diagrams ............................................................ 17 sales, solutions, and legal information ........................ 20 worldwide sales and design supp ort............. ............ 20 products ...................................................................... 20 [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 3 of 21 pinouts figure 1. pin diagram - 32-pin soic and 48-pin ssop table 1. pin definitions pin name alt i/o type description a 0 ?a 16 input address inputs. used to select one of the 131, 072 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data io lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the io pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip. wh en high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . hsb input or output hardware store busy (hsb ) . when low, this output indicates a hardware store is in progress. when pulled low external to the chip, it initiate s a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . this pin is not connected to the die. v cap a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 v cc a 15 hsb we a 13 a 8 a 9 a 11 oe a 10 ce dq 7 dq 6 dq 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 v ss dq 2 dq 3 dq 4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 16 nc dq7 dq6 dq5 nc dq4 v cc dq3 dq2 dq1 dq0 v ss a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 nc hsb we nc nc a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 top view (not to scale) oe ce v cc v ss v cap nc nc nc nc nc nc nc nc nc [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 4 of 21 device operation the cy14b101l nvsram is made up of two functional compo- nents paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation) or from the nonvolatile cell to sram (the recall operation). this unique arch itecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b101l supports unlimited reads and writes similar to a typical sram. in addition, it provides unlimited recall opera- tions from the nonvolatile cells and up to one million store operations. sram read the cy14b101l performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?16 determines the 131,072 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data out puts repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must rema in stable until either ce or we goes high at the end of the cycle. the data on the common io pins dq 0?7 are written into the memory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entir e write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b101l stores data to nvsram using one of three storage operations: 1. hardware store activated by hsb 2. software store activated by an address sequence 3. autostore on device power down autostore operation is a uni que feature of quantumtrap technology and is enabled by default on the cy14b101l. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store ope ration. refer to the dc electrical characteristics on page 8 for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull up is placed on we to hold it inactive during power up. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored, unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. an optional pull-up resist or is shown connected to hsb . the hsb signal is monitored by th e system to detect if an autostore cycle is in progress. hardware store (hsb ) operation the cy14b101l provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the cy14b101l conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram takes place since the last store or recall cycle. the hsb pin also acts as an open dr ain driver that is internally driven low to indicate a busy condition, while the store (initiated by any means) is in progress. this pin should be exter- nally pulled up if it is used to drive other inputs. sram read and write operations, that are in progress when hsb is driven low by any means, are given time to complete before the store operation is initiated. after hsb goes low, the cy14b101l continues sram operations for t delay . during t delay , multiple sram read operatio ns take place. if a write is in progress when hsb is pulled low, it allows a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. if hsb is not used, it is left unconnected. figure 2. autostore mode v cc v cc v cap v cap we 10k ohm 0.1 f u [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 5 of 21 hardware recall (power up) during power up or after any low power condition (v cc < v switch ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. software store data is transferred from the sram to the nonvolatile memory by a software address sequence. the cy14b101l software store cycle is initiated by executing sequential ce controlled read cycles from six specific a ddress locations in exact order. during the store cycle, an eras e of the previ ous nonvolatile data is first performed followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence is performed: 1. read address 0x4e38, valid read 2. read address 0xb1c7, valid read 3. read address 0x83e0, valid read 4. read address 0x7c1f, valid read 5. read address 0x703f, valid read 6. read address 0x8fc0, initiate store cycle the software sequence is clocked with ce controlled reads or oe controlled reads. when the si xth address in the sequence is entered, the store cycle commences and the chip is disabled. it is important that read cycles and not write cycles are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x4e38, valid read 2. read address 0xb1c7, valid read 3. read address 0x83e0, valid read 4. read address 0x7c1f, valid read 5. read address 0x703f, valid read 6. read address 0x4c63, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared, and then the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is once again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. data protection the cy14b101l protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the cy14b101l is in a write mode (both ce and we are low) at power up after a recall or after a store, the write is inhibited until a negat ive transition on ce or we is detected. this protects against inadvertent writ es during power up or brown out conditions. noise considerations the cy14b101l is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. low average active power cmos technology provides the cy14b101l the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. figure 3 shows the relationship between i cc and read or write cycle time. wors t case current consumption is shown for both cmos and ttl input levels (commercial temper- ature range, vcc = 3.6v, 100% duty cycle on chip enable). only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14b101l depends on the following items: the duty cycle of chip enable the overall cycle rate for accesses the ratio of reads to writes cmos versus ttl input levels the operating temperature the v cc level io loading figure 3. current versus cycle time [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 6 of 21 preventing store disable the autostore function by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, perform the following sequence of ce controlled read operations: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable re-enable the autostore by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, perform the following sequence of ce controlled read operations: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) is issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled. best practices nvsram products have been used effectively for over 15 years. while ease of use is one of th e product?s main system values, experience gained working with h undreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configurat ion, cold or warm boot status, and so on must always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, the best practice is to again rewrite the nvsram into the desired state as a safeguard agai nst events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). if autostore is firmware disabled, it does not reset to ?autostore enabled? on every power down event captured by the nvsram. the application firmware should re-enable or re-disable autostore on each reset sequence based on the behavior desired. the v cap value specified in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because higher inrush currents may reduce the reliability of the internal pass transistor. customers that want to use a larger v cap value to make sure there is extra store charge should discuss their v cap size selection with cypress to understand any impact on the vcap voltage level at the end of a t recall period. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 7 of 21 . table 2. hardware mode selection ce we oe a 15 ? a 0 mode io power h x x x not selected output high z standby l h l x read sram output data active [3] l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [2, 3, 4] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [2, 3, 4] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [2, 3, 4] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [2, 3, 4] notes 2. the six consecutive address locations are in the order listed. we is high during all six cycles to enable a nonvolatile cycle. 3. while there are 17 address lines on the cy14b101l, only the lower 16 lines are used to control software modes. 4. io state depends on the state of oe . the io table shown is based on oe low. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 8 of 21 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage on v cc relative to gnd ..........?0.5v to 4.1v voltage applied to outputs in high z state ....................................... ?0.5v to v cc + 0.5v input voltage...........................................?0.5v to vcc + 0.5v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount lead soldering temperature (3 seconds) .......................................... +260 c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage....... ........... ............ ............ > 2001v (mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial -40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) [5, 6] parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial 65 55 50 ma ma industrial 70 60 55 ma ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 6ma i cc3 average v cc current at t rc = 200 ns, 5v, 25c typical we > (v cc ? 0.2v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 10 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 3ma i sb v cc standby current ce > (v cc ? 0.2v). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after n onvolatile cycle is complete. inputs are static. f = 0 mhz. 3ma i ix input leakage current v cc = max, v ss < v in < v cc -1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il -1 +1 a v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and vss, 6v rated. 17 120 uf data retention and endurance parameter description min unit data r data retention at 55 c2 0 y e a r s nv c nonvolatile store operations 200 k notes 5. the hsb pin has i out = ?10 a for v oh of 2.4 v. this parameter is characterized but not tested. 6. v ih changes by 100 mv when v cc > 3.5v. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 9 of 21 capacitance in the following table, the capacitance parameters are listed. [7] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [7] parameter description test conditions 32-soic 48-ssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 33.64 32.9 c/w jc thermal resistance (junction to case) 13.6 16.35 c/w figure 4. ac test loads ac test conditions 3.0v output 30 pf r1 577 r2 789 3.0v output 5 pf r1 577 r2 789 for tri-state specs input pulse levels .................................................... 0v to 3v input rise and fall times (10% to 90%) ...................... < 5 ns input and output timing referenc e levels ...... .............. 1.5v note 7. these parameters are guaranteed by design and are not tested. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 10 of 21 ac switching characteristics sram read cycle parameter description 25 ns [1] 35 ns 45 ns unit min max min max min max cypress parameter alt t ace t elqv chip enable access time 25 35 45 ns t rc [8] t avav, t eleh read cycle time 25 35 45 ns t aa [9] t avqv address access time 25 35 45 ns t doe t glqv output enable to data valid 12 15 20 ns t oha [9] t axqx output hold after address change 3 3 3 ns t lzce [10] t elqx chip enable to output active 3 3 3 ns t hzce [10] t ehqz chip disable to output inactive 10 13 15 ns t lzoe [10] t glqx output enable to output active 0 0 0 ns t hzoe [10] t ghqz output disable to output inactive 10 13 15 ns t pu [7] t elicch chip enable to power active 0 0 0 ns t pd [7] t ehiccl chip disable to power standby 25 35 45 ns switching waveforms figure 5. sram read cycle 1: address controlled [8, 9, 11] figure 6. sram read cycle 2: ce and oe controlled [8, 11] w 5& w $$ w 2+$ $''5(66 '4'$7$287 '$7$9$/,' $''5(66 w 5& &( w $&( w /=&( w 3' w +=&( 2( w '2( w /=2( w +=2( '$7$9$/,' $&7,9( 67$1'%< w 38 '4'$7$287 ,&& notes 8. we and hsb must be high during sram read cycles. 9. device is continuously selected with ce and oe both low. 10. measured 200 mv from steady state output voltage. 11. hsb must remain high during read and write cycles. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 11 of 21 sram write cycle parameter description 25 ns [1] 35 ns 45 ns unit min max min max min max cypress parameter alt t wc t avav write cycle time 25 35 45 ns t pwe t wlwh, t wleh write pulse width 20 25 30 ns t sce t elwh, t eleh chip enable to end of write 20 25 30 ns t sd t dvwh, t dveh data setup to end of write 10 12 15 ns t hd t whdx, t ehdx data hold after end of write 0 0 0 ns t aw t avwh, t aveh address setup to end of write 20 25 30 ns t sa t avwl, t avel address setup to start of write 0 0 0 ns t ha t whax, t ehax address hold after end of write 0 0 0 ns t hzwe [10,12] t wlqz write enable to output disable 10 13 15 ns t lzwe [10] t whqx output active after end of write 3 3 3 ns switching waveforms figure 7. sram write cycle 1: we controlled [12, 13] figure 8. sram write cycle 2: ce and oe controlled [12, 13] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 12. if we is low when ce goes low, the outputs remain in the high impedance state. 13. ce or we must be greater than v ih during address transitions. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 12 of 21 autostore or power up recall parameter alt description cy14b101l unit min max t hrecall [14] t restore power up recall duration 20 ms t store [15, 16] t hlhz store cycle duration 12.5 ms v switch low voltage trigger level 2.65 v t vccrise v cc rise time 150 s switching waveforms figure 9. autostore/power up recall v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise note read and write cycles are ignored during store, recall, and while vcc is below v switch notes 14. t hrecall starts from the time v cc rises above v switch . 15. if an sram write has not taken place since the last nonvolatile cycle, no store will take place. 16. industrial grade devices requires 15 ms max. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 13 of 21 software controlled store/recall cycle the software controlled store/recall cycle follows. [17, 18] parameter alt description 25 ns [1] 35 ns 45 ns unit min max min max min max t rc [18] t avav store/recall initiation cycle time 25 35 45 ns t sa t avel address setup time 0 0 0 ns t cw t eleh clock pulse width 20 25 30 ns t ha t ghax, t elax address hold time 1 1 1 ns t recall recall duration 120 120 120 s switching waveforms figure 10. ce controlled software store/recall cycle [18] figure 11. oe controlled software store/recall cycle [18] t rc t rc t sa t sce t ha t store / t recall data valid data valid 6#sserdda 1#sserdda high impedance address ce oe dq (data) t rc t rc 6#sserdda 1#sserdda address t sa t sce t ha t store / t recall data valid data valid high impedance ce oe dq (data) notes 17. the software sequence is clocked on the falling edge of ce controlled reads or oe controlled reads. 18. the six consecutive addr esses must be read in the order listed in the mode selection table. we must be high during all six consecutive cycles. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 14 of 21 hardware store cycle parameter alt description cy14b101l unit min max t phsb t hlhx hardware store pulse width 15 ns t delay [19] t hlqz , t blqz time allowed to complete sram cycle 1 70 s t ss [20, 21] soft sequence processing time 70 us switching waveforms figure 12. hardware store cycle figure 13. soft sequence processing [20, 21] 3+6% $gguhvv $gguhvv $gguhvv $gguhvv 6riw6htxhqfh &rppdqg w 66 w 66 &( $gguhvv 9 && w 6$ w &: 6riw6htxhqfh &rppdqg w &: notes 19. on a hardware store initiation, sram operation continues to be enabled for time t delay to allow read and write cycles to complete. 20. this is the amount of time to take action on a soft sequence command. vcc power must remain high to effectively register com mand. 21. commands such as store and recall lock out i/o until operation is complete which further increases this time. see specific c ommand. [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 15 of 21 ordering information these parts are not recommended for new designs. speed (ns) ordering code package diagram operating voltage range package type operating range 25 cy14b101l-sz25xct 51-85127 2.7v to 3.6v 32-pin soic commercial cy14b101l-sz25xc 51-85127 2.7v to 3.6v 32-pin soic cy14b101ll-sp25xct 51-85061 2.7v to 3.6v 48-pin ssop cy14b101ll-sp25xc 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sz25xit 51-85127 3.0v to 3.6v 32-pin soic industrial cy14b101l-sz25xi 51-85127 3.0v to 3.6v 32-pin soic cy14b101l-sp25xit 51-85061 3.0v to 3.6v 48-pin ssop cy14b101l-sp25xi 51-85061 3.0v to 3.6v 48-pin ssop option t - tape and reel blank - std. speed 25 - 25 ns 35 - 35 ns 45 - 45 ns package sz - 32 soic sp - 48 ssop data bus l - x8 density 101 - 1 mb voltage b - 3.0v cypress part numbering nomenclature cy 14 b 101 l - sz 25 x c t nvsram 14 - autostore + software store + hardware store temperature c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 16 of 21 35 CY14B101L-SZ35XCt 51-85127 2.7v to 3.6v 32-pin soic commercial CY14B101L-SZ35XC 51-85127 2.7v to 3.6v 32-pin soic cy14b101l-sp35xct 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sp35xc 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sz35xit 51-85127 2.7v to 3.6v 32-pin soic industrial cy14b101l-sz35xi 51-85127 2.7v to 3.6v 32-pin soic cy14b101l-sp35xit 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sp35xi 51-85061 2.7v to 3.6v 48-pin ssop 45 cy14b101l-sz45xct 51-85127 2.7v to 3.6v 32-pin soic commercial cy14b101l-sz45xc 51-85127 2.7v to 3.6v 32-pin soic cy14b101l-sp45xct 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sp45xc 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sz45xit 51-85127 2.7v to 3.6v 32-pin soic industrial cy14b101l-sz45xi 51-85127 2.7v to 3.6v 32-pin soic cy14b101l-sp45xit 51-85061 2.7v to 3.6v 48-pin ssop cy14b101l-sp45xi 51-85061 2.7v to 3.6v 48-pin ssop all parts are pb-free. the above table contains final information . please contact your local cypress sales representative for a vailability of these parts ordering information these parts are not recommended for new designs. speed (ns) ordering code package diagram operating voltage range package type operating range [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 17 of 21 package diagrams figure 14. 32-pin ( 300 mil) soic (51-85127) 51-85127 *b [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 18 of 21 figure 15. 48-pin shrunk small outline package (51-85061) package diagrams (continued) 51-85061 *d [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 19 of 21 document history page document title: cy14b101l 1 mbit (128k x 8) nvsram document number: 001-06400 rev. ecn no. orig. of change submission date description of change ** 425138 tup see ecn new data sheet *a 437321 tup see ecn show data sheet on external web *b 471966 tup see ecn changed i cc3 from 5 ma to 10 ma changed isb from 2 ma to 3 ma changed v ih(min) from 2.2v to 2.0v changed t recall from 40 s to 50 s changed endurance from 1 million cycles to 500k cycles changed data retention from 100 years to 20 years added soft sequence processing time waveform updated part numbering nomenclature and ordering information *c 503272 pci see ecn changed from advance to preliminary changed the term ?unlimited? to ?infinite? changed endurance from 500k cycles to 200k cycles added temperature specif ication to data retention - 20 years at 55 c removed icc 1 values from the dc table for 25 ns and 35 ns industrial grade changed icc 2 value from 3 ma to 6 ma in the dc table added a footnote on v ih changed v switch(min) from 2.55v to 2.45v added footnote 17 related to using the software command updated part nomenclature tabl e and ordering information table *d 597002 tup see ecn removed v switch(min) specification from the autostore/power up re- call table changed t glax specification from 20 ns to 1 ns added t delay(max) specification of 70 s in the hardware store cycle table removed t hlbl specification changed t ss specification from 70 s (min) to 70 s (max) changed v cap(max) from 57 f to 120 f *e 688776 vkn see ecn added footnote related to hsb changed t glax to t ghax *f 1349963 uha/sfv see ecn changed from preliminary to final updated ordering information table *g 2427986 gvch see ecn move to external web *h 2546756 gvch/aesa 08/01/2008 aligned part number nomenclature corrected typo in ordering information changed pin definition of nc pin updated data sheet template [+] feedback not recommended for new designs
cy14b101l document number: 001-06400 rev. *m page 20 of 21 *i 2625139 gvch/pyrs 01/30/09 updated ?features? added data retention at 55 o c updated we pin description added best practices added i cc1 spec for 25ns and 35ns access speed for industrial temper- ate updated v ih from vcc+0.3 to vcc+0.5 removed footnote 4 and 5 added data retention and endurance table added thermal resistance values changed parameter t as to t sa changed t recall from 50us to 120us (including t ss of 70us) renamed t glax to t ha updated figure 11 and 12 renamed t hlhx to t phsb updated figure 13 *j 2695908 gvch/aesa 04/20/2009 removed part numbers cy14b101l-sp25xc and cy14b101l-sp25xct. added part numbers cy14b101ll-sp25xc and cy14b101ll-sp25xct. *k 2814390 gvch 11/25/2009 added note in the orderi ng information section mentioning that these parts are not recommended for new designs. added ?not recommended for new designs? watermark in the pdf. *l 2895330 gvch 03/18/2010 added foot note 1 for 25ns access speed. updated package diagrams. added operating voltage range column to ordering information. *m 2902517 gvch 03/31/2010 added watermark "not recommended for new designs" in pdf version. move to external web. document title: cy14b101l 1 mbit (128k x 8) nvsram document number: 001-06400 rev. ecn no. orig. of change submission date description of change [+] feedback not recommended for new designs
document number: 001-06400 rev. *m revised april 5, 2010 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14b101l ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback not recommended for new designs

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